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devilhunter

RROD when CPU_RST is connected to a glitch Chip

By devilhunter, in Other topics

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devilhunter    11

devilhunter
Posted

My console works fine on retail nand with all glitch wires connected except for CPU_RST. The moment I connect the wire to the glitching chip it gives RROD 0022, I tried the alternative point on the resistor near the CPU die and same issue. Any clue is highly appreciated. 

https://s10.postimg.org/atgn0v0rp/IMAG0047.jpg

 

https://s10.postimg.org/b63svwhcp/IMAG0040.jpg
https://s10.postimg.org/zb4idm1nd/IMAG0041.jpg
https://s10.postimg.org/6a0647h7d/IMAG0042.jpg

Regards. 

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Swizzy    2084

Swizzy
Posted

You need a rgh image for it to work once you've gone past version 16###

Sent from my SM-G903F

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devilhunter    11

devilhunter
Posted

Im at the wiring process, something is shorting and I dont know what is it. If I write the ecc files, the green led (debug) will be pulsing rapidly. 

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Swizzy    2084

Swizzy
Posted

Im at the wiring process, something is shorting and I dont know what is it. If I write the ecc files, the green led (debug) will be pulsing rapidly.

How rapidly? Most likely you missed something with the install, which version of hack are you trying to install?

Sent from my SM-G903F

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gavin_darkglider    1562

gavin_darkglider
Posted

Not sure what you are doing with the wiring, or which hack you are trying to use, but I had similar problems with a falcon, if I would attach CPU_PLL_Bypass it wouldnt boot stock, even with the chip disabled. As for your wiring, as seen in the images is a mess. You have 2 wires going to 3v3 on the clone coolrunner, and pad D isnt attached to anything, which should be CPU_RST. Also, not sure what you are doing on the header next to the chip, as for RGH1/RGH1.2/R-JTOP/R-JTAG+ you only need 3v3 or 5v depending on chip from there, ground goes to AV, unless that is what the second wire is for. Also, dont know if you noticed, it looks like the 3v3 and gnd pad on the coolrunner might be bridged. this is what I am getting just by looking at your wiring so far. That doesnt include nand wiring, as I havnt seen that yet. As for the wiring issue, try running booting the system with the coolrunner in prg mode, and the stock nand. Do not connect JR-P/NandX to the chip for programming, and see if it boots stock with the wires in place.

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devilhunter    11

devilhunter
Posted

How rapidly? Most likely you missed something with the install, which version of hack are you trying to install?

Sent from my SM-G903F

 

Im following RGH 1.2 wiring. I should also note I have RGHed two consoles already. 

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devilhunter    11

devilhunter
Posted

Not sure what you are doing with the wiring, or which hack you are trying to use, but I had similar problems with a falcon, if I would attach CPU_PLL_Bypass it wouldnt boot stock, even with the chip disabled. As for your wiring, as seen in the images is a mess. You have 2 wires going to 3v3 on the clone coolrunner, and pad D isnt attached to anything, which should be CPU_RST. Also, not sure what you are doing on the header next to the chip, as for RGH1/RGH1.2/R-JTOP/R-JTAG+ you only need 3v3 or 5v depending on chip from there, ground goes to AV, unless that is what the second wire is for. Also, dont know if you noticed, it looks like the 3v3 and gnd pad on the coolrunner might be bridged. this is what I am getting just by looking at your wiring so far. That doesnt include nand wiring, as I havnt seen that yet. As for the wiring issue, try running booting the system with the coolrunner in prg mode, and the stock nand. Do not connect JR-P/NandX to the chip for programming, and see if it boots stock with the wires in place.

mine does boot to stock only if the CPU_RST isnt connected to the chip, I cleaned flux residue thanks for pointing it out. Im trying to RGH the console (RGH 1.2) since CR4 XL didnt work for me ( bad recent batch) this is why I switched to clones. 

 

Thanks a lot. 

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gavin_darkglider    1562

gavin_darkglider
Posted

Did you disable the chip and see if it booted stock with the wires in place? Even if it doesnt boot, try flashing ecc, and try it anyway, as I said I have had consoles not boot stock due to wires adding interference, which throws off the sys checks that are done on startup. you might look into the cpu_rst_cleaner, if the problem persists.

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devilhunter    11

devilhunter
Posted

I disabled the chip, same problem. For your information, you dont have to disable the chip on phats; they are going to run with a single glitch pulse if all wiring are good.

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gavin_darkglider    1562

gavin_darkglider
Posted

I disabled the chip, same problem. For your information, you dont have to disable the chip on phats; they are going to run with a single glitch pulse if all wiring are good.

I know that..... it is part of my diagnostic process. As if it is connected, and still doesnt work with the chip disabled.... As I said previously, I have had them get rrod 0022 on stock with the wires connected, usually PLL_BYPASS, but interference on cpu_rst could cause this issue also. I would write ecc, and see if I could get it to boot xell, even with stock rrod. if you can get it to boot as a glitch console, I would suggest either moving the chip to the heatsync, for shortest possible length of wire, or looking into double shielded cable, and or cpu_rst_cleaner, as you said it worked when the wire is disconnected from the chip. also hooking up a post out monitor would be helpfull for the diagnostic process.

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devilhunter    11

devilhunter
Posted

Tried matrix chip today, same shit.

 

Thanks a lot, very informative post. I have the cpu double shielded wire, which CPU_RST point I should use? Also, why would PLL interfere with CPU_RST? In order to eliminate this possibility I rerouted the cpu wire from the fans side to the chip. 

I left the console for hours, never it did boot to xell. One more thing, what do you mean by post monitor? 

 

RST soldering:

 

IMAG0051.jpg
 
IMAG0052.jpg
 
IMAG0053.jpg
 
IMAG0054.jpg
 

Thanks a lot. 

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Swizzy    2084

Swizzy
Posted (edited)

I disabled the chip, same problem. For your information, you dont have to disable the chip on phats; they are going to run with a single glitch pulse if all wiring are good.

Only pre 16k, with 16k+ dashboards you have the new bootloader with random timings causing the glitch pulse to mess it up

** edit: **

What i would try is hook everything up, then remove POST_OUT and see if it works, if it does, great! there should be nothing wrong with the install...

Edited by Swizzy

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devilhunter    11

devilhunter
Posted

Will check for the dashboard now, as for the post_out. It only works when the CPU_RST is removed.

 

Edit:

 

actually, it boots normally now with the CR3 off and and the clk point removed!! I never thought of that. Attaching a picture of my alternative point.

 

IMAG0058.jpg

 

Dash board is the latest. 

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gavin_darkglider    1562

gavin_darkglider
Posted

Post out monitor was included with some chips from TX(CR3/4/R-JTag to be specific), but would monitor post codes that would allow you to see where the console is failing in the boot cycle. there have been a few homebrew implementations for full post consoles, which all phat consoles are.

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devilhunter    11

devilhunter
Posted

Post out monitor was included with some chips from TX(CR3/4/R-JTag to be specific), but would monitor post codes that would allow you to see where the console is failing in the boot cycle. there have been a few homebrew implementations for full post consoles, which all phat consoles are.

At this point, Im assuming you need a log. Will try to get that. 

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devilhunter    11

devilhunter
Posted

Here is my log file: 

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post BF 
Post 9F - Panic - VERIFY_SECOTP_5 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 99 
Post 19 - HMACSHA_COMPUTE 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 01 
Post 40 - Entrypoint of CD reached 
Post 60 - INIT_KERNEL 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post E6 
Post FE 
Post BF 
Post 9F - Panic - VERIFY_SECOTP_5 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 99 
Post 19 - HMACSHA_COMPUTE 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 01 
 
 
 
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 6F - INIT_POWER_MODE 
Post 0F 
Post 07 
Post 03 
Post 01 
Post 10 - Payload/1BL started 
Post 90 - Panic - VMX_ASSIST 
Post D0 - CB_A entry point reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post FC 
Post FE 
Post 7F 
Post 2F - RELOCATE 
Post 0F 
Post 07 
Post 03 
Post 01 
Post 80 
 
 
 
 
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 6F - INIT_POWER_MODE 
Post 0F 
Post 07 
Post 03 
Post 01 
Post 10 - Payload/1BL started 
Post 90 - Panic - VMX_ASSIST 
Post D0 - CB_A entry point reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post FC 
Post FE 
Post 7F 
Post 2F - RELOCATE 
Post 0F 
Post 07 
Post 03 
Post 01 
Post 80 
Shutdown
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 64 - INIT_MEMORY_MANAGER 
Post 74 - INIT_SHADOWBOOT 
Post 7C 
Post 7E 
Post FE 
Post FE 
Post FC 
Post F4 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 70 - INIT_VIDEO_DRIVER 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 70 - INIT_VIDEO_DRIVER 
Post F4 
Post FC 
Post FE 
Post FC 
Post F4 
Post FE 
Post FC 
Post 40 - Entrypoint of CD reached 
Post E0 
Post FC 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post 40 - Entrypoint of CD reached 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post CF 
Post 38 - SIG_VERIFY_4BL_CD 
Post EF 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post CF 
Post FC 
Post EF 
Post EF 
Post 10 - Payload/1BL started 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 70 - INIT_VIDEO_DRIVER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 01 
Post 10 - Payload/1BL started 
Post 04 
Post FB 
Post 04 
Post 80 
Post 20 - CB entry point reached 
Post DF 
Post CF 
Post FE 
Post 20 - CB entry point reached 
Post 70 - INIT_VIDEO_DRIVER 
Post FC 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 70 - INIT_VIDEO_DRIVER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 70 - INIT_VIDEO_DRIVER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 70 - INIT_VIDEO_DRIVER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 10 - Payload/1BL started 
Post 50 - LOAD_UPDATE_1 
Post 70 - INIT_VIDEO_DRIVER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 10 - Payload/1BL started 
Post 50 - LOAD_UPDATE_1 
Post 70 - INIT_VIDEO_DRIVER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 10 - Payload/1BL started 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 40 - Entrypoint of CD reached 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Shutdown
 

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Swizzy    2084

Swizzy
Posted

i assume this is with a single bit post? that's not going to help much, you need full post to get any real information from it...

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devilhunter    11

devilhunter
Posted

well, this is as much as I could get with the fake coolrunner   :X , the console boots fine on retail, I can sell it and get another shit :D

 

I do have a jtagable jasper, why the fuck I have to get RGH anways 

 

I might start doing consols mod, Im confident enough with my installs, I did two rgh and they boot from first or the second glitch attempt. This one in particular is asshole 

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gavin_darkglider    1562

gavin_darkglider
Posted

You say it boots stock if you remove the standby clk from the board also? if so try the standard clk point on the topside of the board, or try hooking up a seperate crystal, like on the carona consoles. just some other ideas.

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devilhunter    11

devilhunter
Posted

Smart move gavin, I also should mention I have a CR4, maybe I can use that for post.

 

Should I be using RGH 1.2 connections or Im forced with R-Jtag?

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gavin_darkglider    1562

gavin_darkglider
Posted

cr-4 is fake post, full post is better. I would try the r-jtag+ on the cr4, as it umight ses the same points, as rgh1.2, and if it boots stock with the wires connected, it might indicate a faulty coolrunner also. you could probably leave jtag wiring out for that test. It should still boot stock with cr4 connected, and stock image.

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