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ronsonol

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Posts posted by ronsonol


  1. 59 minutes ago, Octal450 said:

    @ronsonol

    Here: https://mega.nz/file/TQMl1QLI#kWMv2BRHFMI-ynnPjc4qFkwTNre1_O3tNIJDzB0AJYM

    Try this. Should work. If it does I'll make a few 150's to tune more.

    Kind Regards,

    Josh

    @Octal450

    Awesome.  It works!  I think it might be working better than the one I was using before - but it's at least on par.  Hard to tell with limited testing over my lunch hour.

    I only tried a few attempts so far; To the dash 12, 6 and 4.  To Xell 4, and 3. 

    So it seems my ace chip is only happy with the 150's.  Thanks for the help.


  2. Hello Josh,

    thanks for all the great work you do supporting this platform.  I really enjoy your videos.  I recently did a RGH2 on a Zephyr following your online guide.

    I made a couple observations along the way. 

    First I could not get Xell to load at all using the timing files built into your latest release.  I can't say I tried them all but I did try at least most of them.  I also was patient, very patient, in my attempts trying each timing file for a few times.  So I literally a couple hours trying different ones which I was prepared for given that it was a Zephyr.  I am using the latest release V3.0.0d.  Then I found a download from another Youtuber with 4 files in it.  2 labeled zephyr_150 and 2 zephyr_300.  It was the second file I tried that worked zephyr_150_E_2_L_1.xsvf to boot Xell.  My ace v3 clock says 150MHz, not sure what bundled timing file are 150 vs 300.

    While booting times are sort of inconsistent it does at least boot, sometimes 1st glitch and often 7 to 15 or more attempts.  So I don't know what is different about this timing file and the ones included in your J-runner release.  One thing I noticed is that my board has a label Rev A on it, and it has populated the big capacitor right beside the top Alt Rst point whereas the picture of your board online does not.

    Also when I built the nand I did check SMC+, but I don't think I am seeing quicker glitching attempts.  The online guide says you can enable it, but the J-runner hint that pops up says for RGH 1.2 and S-RGH. 

    I have selected Falcon as the board type during both image build attempts.  In the xebuild log file I see difference in the build when this is enable vs not. 

    Under the Section labelled: Encrypting and finalizing bootloaders binary!

    With SMC+ enabled; 

    encoding SMC.bin size 0x3000
    SMC checksum: df1fff40
    unknown SMC found, type: Falcon v3.1(1.06)
    glitch hack found in SMC binary!

    Without SMC+ enabled; 

    encoding smc.bin size 0x3000
    SMC checksum: 7e5bc217
    known clean SMC found, type: Zephyr v2.1(1.13)
    patching SMC reset limit at offset: 0x12a3
    SMC reset limit patched successfully!

    Many thanks for all the support.

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